It has been a consistent goal of the semiconductor industry to provide smaller high speed Random Access Memory (RAM) chips. Much work has been done in MOS technology, but the goal has always been to reduce costs along with size commensurate with adequate operating speed. Another goal of the industry which has been met with MOS techniques is the reduction of power, both in terms of standby and operating consumption. But the present state of the art does not provide a low power, relatively high speed, low cost circuit which has a very high packing density.